Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base

ABSTRACT

Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

BACKGROUND

The invention relates generally to semiconductor device fabrication and,in particular, to device structures for a bipolar junction transistor,as well as fabrication methods and design structures for a bipolarjunction transistor.

Bipolar junction transistors are three-terminal electronic devices thatinclude three semiconductor regions defining an emitter, an intrinsicbase, and a collector. An NPN bipolar junction transistor includes tworegions of n-type semiconductor material constituting the emitter andcollector, and a region of p-type semiconductor material sandwichedbetween the two regions of n-type semiconductor material to constitutethe intrinsic base. A PNP bipolar junction transistor includes tworegions of p-type semiconductor material constituting the emitter andcollector, and a region of n-type semiconductor material sandwichedbetween the two regions of p-type semiconductor material to constitutethe base. The differing conductivity types of the emitter, base, andcollector define a pair of p-n junctions, namely a collector-basejunction and an emitter-base junction, across which the conductivitytype changes. A voltage applied across the emitter-base junctioncontrols the movement of charge carriers that produces charge flowbetween the collector and emitter.

Bipolar junction transistors may be found, among other end uses, inhigh-frequency and high-power applications. In particular, bipolarjunction transistors may be used in radiofrequency integrated circuits,which are found in wireless communications systems, power amplifiers inmobile devices, and other varieties of high-speed end uses.

Improved device structures, fabrication methods, and design structuresare needed for bipolar junction transistors.

SUMMARY

In an embodiment of the invention, a method is provided for forming adevice structure for a bipolar junction transistor. The method includesforming an intrinsic base layer on a semiconductor substrate, forming anetch stop layer on the intrinsic base layer, and forming an extrinsicbase layer on the etch stop layer. The method further includes forming atrench penetrating through the extrinsic base layer to the etch stoplayer. The trench is formed by etching the extrinsic base layerselective to the etch stop layer. The method further includes extendingthe trench through the etch stop layer to the intrinsic base layer byetching the etch stop layer selective to the intrinsic base layer. Afterthe trench is extended through the etch stop layer, an emitter is formedusing the trench.

In an embodiment of the invention, a method is provided for forming adevice structure for a bipolar junction transistor. The method includesforming an intrinsic base layer on a semiconductor substrate and formingan extrinsic base layer on the intrinsic base layer. The method furtherincludes forming a trench penetrating through the extrinsic base layerto the intrinsic base layer by etching the extrinsic base layerselective to the intrinsic base layer. After the trench is formed, anemitter is formed in the trench.

In an embodiment of the invention, a hardware description language (HDL)design structure is encoded on a machine-readable data storage medium.The HDL design structure comprises elements that, when processed in acomputer-aided design system, generates a machine-executablerepresentation of a bipolar junction transistor. The HDL designstructure includes an intrinsic base, an etch stop layer on theintrinsic base, an extrinsic base on the etch stop layer, a trenchpenetrating through the extrinsic base layer and the etch stop layer tothe intrinsic base layer, and an emitter in the trench. The etch stoplayer is comprised of a semiconductor material that etches selective tothe semiconductor material of the extrinsic base and the semiconductormaterial of the intrinsic base. The HDL design structure may comprise anetlist. The HDL design structure may also reside on storage medium as adata format used for the exchange of layout data of integrated circuits.The HDL design structure may reside in a programmable gate array.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments of theinvention and, together with a general description of the inventiongiven above and the detailed description of the embodiments given below,serve to explain the embodiments of the invention.

FIGS. 1-8 are cross-sectional views of a portion of a substrate atsuccessive fabrication stages of a processing method for fabricating adevice structure in accordance with an embodiment of the invention.

FIG. 9 is a cross-sectional view similar to FIG. 6 of a substrateportion for fabricating a device structure in accordance with analternative embodiment of the invention.

FIG. 10 is a cross-sectional view similar to FIG. 3 of a substrateportion for fabricating a device structure in accordance with analternative embodiment of the invention.

FIG. 11 is a cross-sectional view of the substrate portion of FIG. 10 atsubsequent fabrication state.

FIG. 12 is a flow diagram of a design process used in semiconductordesign, manufacture, and/or test.

DETAILED DESCRIPTION

With reference to FIG. 1 and in accordance with an embodiment of theinvention, a substrate 10 comprises a single crystal semiconductormaterial usable to form an integrated circuit. For example, substrate 10may be comprised of a monocrystalline silicon-containing material, suchas a bulk wafer of single crystal silicon or a single-crystal silicondevice layer of a silicon-on-insulator wafer. The semiconductor materialcomprising substrate 10 may be lightly doped to alter its electricalproperties.

A subcollector 12 is defined by a doped region in the substrate 10. Thesubcollector 12 may be formed by introducing an electrically-activedopant, such as an n-type dopant from Group V of the Periodic Table(e.g., phosphorus (P), arsenic (As), or antimony (Sb)) effective toimpart n-type conductivity in the host semiconductor material. In oneembodiment, the subcollector 12 may be formed by ion implantation of then-type dopant with a photolithography-defined mask present and,thereafter, annealing to electrically activate the dopant and toalleviate implantation damage.

The substrate 10 includes an epitaxial layer 14 comprised ofsemiconductor material. The epitaxial layer 14 may be doped in situduring growth by, for example, chemical vapor deposition to have thesame conductivity type as the subcollector 12 and is electricallycontinuous with the subcollector 12. For example, the epitaxial layer 14may be comprised of single crystal silicon epitaxially deposited orgrown by chemical vapor deposition (CVD) and doped with a concentrationof an n-type dopant effective to impart n-type conductivity. The dopantmay be introduced in situ during formation of the epitaxial layer 14 byadding a gas, such as phosphine or arsine, to the CVD reactants. Thesubcollector 12 and epitaxial layer 14 may have an opposite conductivitytype from the bulk of the substrate 10.

Semiconductor layers 16, 18, 20, 22 are formed as continuous additiveset of layers in a layer stack on the top surface of the substrate 10.Prior to deposition of the layer stack, the epitaxial layer 14 may becleaned to, for example, remove native oxide.

The semiconductor layer 16 of the layer stack may be used subsequentlyto form the intrinsic base of the bipolar junction transistor. Thesemiconductor layer 16 The intrinsic base layer 34 may be comprised of asemiconductor material, such as silicon, silicon-germanium (SiGe)including silicon (Si) and germanium (Ge) in a composition with thesilicon content ranging from 95 atomic percent to 50 atomic percent andthe germanium content ranging from 5 atomic percent to 50 atomicpercent, or SiGe:C with a composition having up to 10 percent carbon. Inan embodiment, the intrinsic base layer 34 may be SiGe with a stepped Geprofile, and may be doped with one or more impurity species, such asboron either with or without carbon.

The semiconductor layer 18 of the layer stack has a differentcomposition from the semiconductor layer 16. For example, semiconductorlayer 18 may have a composition that is adjusted during growth to notcontain any germanium (Ge). In one embodiment, the semiconductor layer18 may be entirely comprised of silicon (Si) that is intrinsic. Anintrinsic base of the device structure is collectively formed using thesemiconductor layers 16, 18 and, for that reason, the semiconductorlayers 16, 18 may be considered to be sublayers belonging to a compositeintrinsic base layer and eventually sublayers of a composite intrinsicbase of the bipolar junction transistor.

The semiconductor layer 20 of the layer stack may function in asubsequent process step as an etch stop layer and, for at least thatreason, may have a different composition than the semiconductor layer22. The composition difference is chosen such that an etching processcan be selected that removes semiconductor layer 20 at a much lower ratethan semiconductor layer 22. The compositions of semiconductor layers 18and 20 may also differ. In one embodiment, the semiconductor layer 20may be comprised of a semiconductor material, such as silicon-germanium.

The semiconductor layer 22 of the layer stack may be used subsequentlyto form the extrinsic base of the bipolar junction transistor. Thesemiconductor layer 20 may be comprised of a semiconductor material,such as silicon that contains a dopant effective to impart p-typeconductivity.

The semiconductor layers 16, 18, 20, 22 have an epitaxial relationship.The semiconductor layers 16, 18, 20, 22 may be serially formed using alow temperature epitaxial (LTE) growth process, such asultra-high-vacuum (UHV) chemical vapor deposition (CVD) that may beconducted at a growth temperature ranging from 400° C. to 850° C. Duringepitaxy, the semiconductor layers 16, 18, 20, 22 will acquire thecrystal structure of single crystal material of the substrate 10 and, inparticular, the epitaxial layer 14 of the substrate 10, which serves asa crystalline template during growth.

A top surface of semiconductor layer 16 and a bottom surface ofsemiconductor layer 18 are coextensive along an interface 17. A topsurface of semiconductor layer 18 and a bottom surface of semiconductorlayer 20 are coextensive along an interface 19. A top surface ofsemiconductor layer 20 and a bottom surface of semiconductor layer 22are coextensive along an interface 21. Due at least in part to the useof an epitaxial growth process, the interfaces 17, 19, 21 are planar andthe respective adjacent surfaces of the layers 16, 18, 20 are likewiseflat.

Dielectric layers 24, 26 are formed on a top surface of thesemiconductor layer 22. Dielectric layer 24 may be comprised of anelectrical insulator, such as silicon dioxide (SiO₂) deposited usingCVD. Dielectric layer 26 may be comprised of a different electricalinsulator, such as silicon nitride (Si₃N₄) deposited using CVD, and maybe thinner than dielectric layer 24.

A patterned mask 28 is formed on a top surface of dielectric layer 26.The mask 28 may be comprised of a layer of sacrificial material that isapplied and patterned with photolithography. To that end, the layer maybe comprised of a photoresist that is applied by a spin coating process,pre-baked, exposed to a radiation projected through a photomask, bakedafter exposure, and developed with a chemical developer to form openings29 in the patterned mask 28.

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent fabrication stage of theprocessing method, a dry etch process, such as a reactive ion etch(RIE), may be used to remove unmasked portions of the dielectric layers24, 26 and semiconductor layer 22 to define openings 30, 31, 32 that arein alignment with the openings 29 in the mask 28. The etch process istimed so that the openings 30, 31, 32 only penetrate partially throughthe thickness of semiconductor layer 22. Specifically, the openingspenetrate to a depth, d, that is a fraction of the total thickness, t.The peripheral openings 30, 32 are subsequently used to form isolationtrenches and the central opening 31 is subsequently used to form anemitter opening.

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent fabrication stage of theprocessing method, the mask 28 is removed after the openings 30, 31, 32are formed. If comprised of a photoresist, the mask 28 may be removed byashing or solvent stripping, followed by surface cleaning. Optionalspacers (not shown) may be formed inside the openings 30, 31, 32.

An etching process is used to extend the openings 30, 31, 32 through theremaining thickness of the semiconductor layer 22. The remainingthickness is given by the difference between thickness, t, and depth, d(FIG. 2). The etching process stops on the semiconductor layer 20, whichguides the selection of an etching process that removes thesemiconductor layer 22 at a significantly higher rate than thesemiconductor layer 20. An exemplary etching process may be a wetchemical etch using a solution of potassium hydroxide (KOH), potassiumdichromate (K₂Cr₂O₇), propanol, and water that removes siliconcomprising semiconductor layer 22 selective to silicon-germaniumcomprising semiconductor layer 20.

Spacers 34 may be formed inside the openings 30, 31, 32. The spacers 34may be formed by depositing conformal layers comprised of an electricalinsulator, such as a layer of silicon dioxide (SiO₂) and a layer ofsilicon nitride (Si₃N₄), and shaping the conformal layers with one ormore etching process, such as RIE, chemical oxide removal (COR), etc.

With reference to FIG. 4 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent fabrication stage of theprocessing method, an etching process is used to extend the openings 30,31, 32 through the semiconductor layer 20. The etching process stops onthe semiconductor layer 18, which guides the selection of an etchingprocess that removes the semiconductor layer 20 at a significantlyhigher rate than the semiconductor layer 18. An exemplary etchingprocess may comprise a wet chemical etch using a solution of ammoniumhydroxide (NH₄OH), hydrogen peroxide (H₂O₂), and water (H₂O) or asolution of hydrofluoric acid (HF), nitric acid (HNO₃), and H₂O thatremoves silicon-germanium semiconductor layer 20 selective to siliconsemiconductor layer 18.

A passivation layer, such as a layer of silicon dioxide (SiO₂), isapplied to passivate the surfaces of semiconductor layer 18 exposed atthe bottom of the openings 30, 31, 32. The passivation layer is removedprior to depositing a semiconductor layer 36 that contacts these exposedsurfaces of semiconductor layer 18 at the bottom of the openings 30, 31,32. Chemical oxide removal may be used to remove the passivation layer,if comprised of SiO₂, to provide clean surfaces for the growth of thesemiconductor layer 36.

The semiconductor layer 36 fills the openings 30, 31, 32, issubsequently used to form the emitter of the bipolar junction transistorinside and about opening 31, and is extraneous material inside openings30, 32. The semiconductor layer 36 may be comprised of polysilicondeposited by CVD or low-pressure CVD (LPCVD) and heavily doped with aconcentration of an n-type dopant effective to impart n-typeconductivity. The heavy-doping level reduces the resistivity of thepolysilicon, and may be introduced by in situ doping that adds a dopantgas, such as phosphine or arsine, to the CVD reactant gases. A cap layer38 is then formed to cover the semiconductor layer 36. The cap layer 38may be comprised of an electrical insulator, such as silicon dioxide(SiO₂).

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent fabrication stage of theprocessing method, a patterned mask 40 is formed that covers a sectionof the semiconductor layer 36 that is coextensive with the opening 31.The mask 40 may be comprised of a layer of sacrificial material that isapplied and photolithographically patterned. To that end, the layer maybe comprised of a photoresist that is applied by a spin coating process,pre-baked, exposed to a radiation projected through a photomask, bakedafter exposure, and developed with a chemical developer to form thepatterned mask 40.

A wet chemical etching process may be used to remove portions of the caplayer 38 that are not protected by the patterned mask 40. If the caplayer 38 is comprised of an oxide of silicon, the wet chemical etchingprocess may utilize a wet chemical etchant comprising bufferedhydrofluoric acid (BHF) or diluted hydrofluoric acid (DHF).

An etching process, such as RIE, is used to remove the field regions ofthe dielectric layer 26 and the semiconductor layer 36. Residualportions of layers 26, 36 registered with the opening 31 are protectedby the patterned mask 40 during the etching process. The residualportion of semiconductor layer 36 defines an emitter 42 of the bipolarjunction transistor that has a body 39 that fills the opening 31 andthat has a head 43 outside of the opening. The edges of the head 43 ofthe emitter 42 extend laterally to have a slight overlap with thedielectric layer 24. Portions of semiconductor layer 36 may remain inopenings 30, 32 at the conclusion of the etching process, and remainextraneous material. The portion of semiconductor layer 18 inside ofopening 31 may be considered to define an “i-layer”.

Doped regions 46 are formed as a protective layer at respectivesidewalls 41 of the head 43 of the emitter 42. Energetic ions, asindicated diagrammatically by the single-headed arrows 44, may beintroduced over a shallow depth using an angled ion implantation processto form the doped regions 46. The implantation conditions (e.g., kineticenergy and dose) are selected to form the doped regions 46 with adesired depth profile and doping concentration at the shallow depth. Asused herein, the term “angled implantation” denotes that the iontrajectories impinge the top surface traveling at incident angles thatthan 0°, wherein 0° represents a direction normal (i.e., perpendicular)to the top surface. The implanted dopant may comprise a p-type dopantspecies (e.g., boron), and the doped regions 46 may have an oppositeconductivity type from the bulk of the emitter 42. The mask 40 operatesas an ion-implantation mask that protects the remainder of the emitter42, other than the sidewalls 41, against receiving an implanted dose ofthe ions 44. The properties of the mask 40 are selected to stopimplanted ions from reaching the top surface of the emitter 42. Thesemiconductor layers 16, 18, 20, 22 are also masked during theimplantation.

With reference to FIG. 6 in which like reference numerals refer to likefeatures in FIG. 5 and at a subsequent fabrication stage of theprocessing method, an etching process is used to extend the openings 30,32 through the remaining portions of semiconductor layer 36 in openings30, 32 and the semiconductor layers 16, 18, and to a shallow depth intothe epitaxial layer 14 of the substrate 10. The etching process isselected to remove the semiconductor materials of layers 16, 18, 36selective to the dielectric material(s) comprising dielectric layer 24and cap layer 38. For example, if the dielectric layer 24 and cap layer38 are comprised of silicon dioxide and the semiconductor layers 16, 18,36 are comprised of silicon, the etchant may be selected to etch siliconselective to silicon dioxide. After the conclusion of the etchingprocess, the mask 40 is removed. If comprised of a photoresist, the mask40 may be removed by ashing or solvent stripping, followed by surfacecleaning.

With reference to FIG. 7 in which like reference numerals refer to likefeatures in FIG. 6 and at a subsequent fabrication stage of theprocessing method, isolation regions 50 are formed in the substrate 10and undercut the semiconductor layer 16. Each isolation region 50 mayhave the form of an airgap, which may be characterized by an effectivedielectric constant of near unity (about 1.0). The isolation regions 50may be filled by air at or near atmospheric pressure, filled by anothergas at or near atmospheric pressure, or contain air or another gas at asub-atmospheric pressure (e.g., a partial vacuum). The isolation regions50 may be connected to form a continuous air gap.

To form the isolation regions 50, the semiconductor material of thesubstrate 10 may be etched by a wet chemical etching process, a dryetching process, or a combination of wet chemical and dry etchingprocesses selective to the materials of the spacers 34, thesemiconductor layer 16, the shallow doped regions 46 in the sidewalls 41of the head 43 of the emitter 42, the cap layer 38, and the dielectriclayer 24. The profile of the isolation regions 50 may be adjusted tohave a specific shape, undercutting angle, undercut distance (i.e.,bias), etc. by selecting factors such as the chemistry, duration, etc.of the etching process. The etching process may be combined withimplantation damage to the semiconductor material and/or doping of thesemiconductor material to alter etch rates and, thereby, the profile.The etching process may further rely on wafer orientation andanisotropic etching processes that exhibit different etch rates fordifferent crystallographic directions (as specified by, for example,Miller indices) in a single-crystal semiconductor material. In oneembodiment, the etching process may be a wet chemical etching processthat is anisotropic and that uses an etchant comprising potassiumhydroxide (KOH), ammonium hydroxide (NH₄OH), tetramethylammoniumhydroxide (TMAH), or ethylenediamine pyrocatechol (EDP).

A passivation layer 48 may be formed that covers the exposed surfacessurrounding the isolation regions 50. The passivation layer 48 may becomprised of a dielectric material, such as an electrical insulator likea high temperature oxide (HTO) grown by either wet or dry thermaloxidation, and serves to passivate the semiconductor materials of theexposed surfaces surrounding the isolation regions 50.

A collector 58 of a bipolar junction transistor 56 is defined in thesubstrate 10 by the portion of the epitaxial layer 14 that is locatedbetween isolation regions 50. The collector 58 may be comprised of thesemiconductor material of the epitaxial layer 14 in its as-grown stateor may receive an additional ion implantation to further enhance itsconductivity. The mask 40 used to form the isolation regions is the samemask that is used to define the head 43 of the emitter 42.

An intrinsic base 60 is defined by the portions of semiconductor layers16, 18 that are between the openings 30, 32 and that are directlyunderneath emitter 42. An extrinsic base 62, which is raised relative tothe intrinsic base 60, is defined by portions of layers 20, 22 betweenthe openings 30, 32 and also portions of layers 16, 18 between theopenings 30, 32 other than their contribution to the intrinsic base 60.The extrinsic base 62 has a planar top surface and a planar bottomsurface because at least in part, it is formed from layers 16, 18, 22that are formed on a planar surface of substrate 10. The body 39 of theemitter 42 and spacers 34 interrupt the continuity of the extrinsic base62. An emitter-base junction 64 is defined at the interface between theemitter 42 and the intrinsic base 60, and a collector-base junction 66is defined at the interface between the intrinsic base 60 and thecollector 58. Due primarily to the use of masked etches to form theopenings 30, 31, 32, the emitter 42, isolation regions 50, collector 58,and intrinsic base 60 are self-aligned relative to each other.

The bipolar junction transistor 56 occupies a device region, which canbe divided into an intrinsic device region coinciding with the portionsof the emitter 42, intrinsic base 60, and collector 58 participating inthe junctions 64, 66, and an extrinsic device region outside of theintrinsic device region. The bipolar junction transistor 56 may becharacterized as a heterojunction bipolar transistor if at least two ofthe emitter 42, collector 58, and intrinsic base 60 are comprised ofdifferent semiconductor materials. In the representative embodiment, thebipolar junction transistor 56 is an NPN bipolar junction transistorthat includes two regions of n-type semiconductor material constitutingthe emitter 42 and collector 58, and a region of p-type semiconductormaterial sandwiched between the two regions of n-type semiconductormaterial to constitute the intrinsic base 60.

During the front-end-of-line (FEOL) portion of the fabrication process,the device structure of the bipolar junction transistor 56 is replicatedacross at least a portion of the surface area of the substrate 10. Alayer of photoresist may be applied to regions of the substrate 10 beingused to form the bipolar junction transistors 56 following thisfabrication stage. Protective layers may be removed from other regionsof the substrate 10 to form complementary metal-oxide-semiconductor(CMOS) field-effect transistors. The order in which the field-effecttransistors and bipolar junction transistors are formed may be reversed.As a result, both bipolar junction transistors and CMOS transistors maybe available on the same substrate 10.

With reference to FIG. 8 in which like reference numerals refer to likefeatures in FIG. 7 and at a subsequent fabrication stage of theprocessing method, field regions of the various layers are removed whilethe emitter 42 and extrinsic base 62 of the bipolar junction transistor56 are protected by a mask layer. The field region removal exposes acontact area 70 comprised of the semiconductor material of the substrate10. The contact area 70 may be used to establish electrical contact withthe collector 58. The spacers 34, cap layer 38, and dielectric layer 24are completely or partially removed.

Standard middle-end-of-line (MEOL) and back-end-of-line (BEOL)processing follows, which includes silicide formation, formation ofcontacts and wiring for the local interconnect structure to the bipolarjunction transistor 56, and formation of dielectric layers, via plugs,and wiring for an interconnect structure coupled by the interconnectwiring with the bipolar junction transistor 56. Other active and passivecircuit elements, such as diodes, resistors, capacitors, varactors, andinductors, may be integrated into the interconnect structure andavailable for use in the integrated circuit.

Sections 72 of a silicide layer are formed on the emitter 42, theextrinsic base 62, and the contact area 70. The sections 72 of thesilicide layer may be formed by a silicidation process that involves oneor more annealing steps to form a silicide phase by reacting a layer ofsilicide-forming metal and the semiconductor material contacting thesilicide-forming metal. Contacts 74 are formed in a layer of insulatingmaterial (not shown) to provide electrical connections with the sections72 of the silicide layer on the contact area 70, the emitter 42 and theextrinsic base 62. The contacts 74 are comprised of a conductor, such asa refractory metal like tungsten (W), which can be clad with aconductive liner (e.g., titanium nitride (TiN)), and the dielectriclayer may be comprised of an electrically-insulating dielectricmaterial, such as borophosphosilicate glass (BPSG).

With reference to FIG. 9 in which like reference numerals refer to likefeatures in FIG. 6 and in accordance with an alternative embodiment ofthe invention, dielectric spacers 78 may be formed as a protective layerat the sidewalls 41 of the head 43 of the emitter 42. The dielectricspacers 78 may be formed by depositing a conformal layer comprised of anelectrical insulator, such silicon nitride (Si₃N₄), and shaping theconformal layer with one or more etching process, such as RIE. Thepresence of the dielectric spacers 78 may eliminate the need to implantions 44 (FIG. 5) to form the shallow doped regions 46 because thedielectric spacers 78 may serve a similar protective function during theetching process forming the isolation regions 50. The process flowcontinues as described in FIGS. 7-8 to form the bipolar junctiontransistor 56.

With reference to FIG. 10 in which like reference numerals refer to likefeatures in FIG. 3 and in accordance with an alternative embodiment ofthe invention, semiconductor layer 20 may be omitted from the layerstack formed on the substrate 10. When the openings 30, 31, 32 areformed, an etching process is used that stops on the semiconductormaterial of semiconductor layer 16. An exemplary etching process maycomprise a wet chemical etch using a solution of potassium hydroxide(KOH), potassium dichromate (K₂Cr₂O₇), propanol, and water that removessilicon selective to silicon-germanium.

With reference to FIG. 11 in which like reference numerals refer to likefeatures in FIGS. 10 and 5 and at a subsequent fabrication stage of theprocessing method, sections 80 of the semiconductor material ofsemiconductor layer 18 are formed by an epitaxial growth process insidethe openings 30, 31, 32 to replace the sections removed by the etchingprocess. In particular, the section 80 of semiconductor layer 18 insideopening 31 separates the emitter 42 from the intrinsic base 60 anddefines the “i-layer”. The process flow continues as described in FIGS.4-8 to form the bipolar junction transistor 56.

FIG. 12 shows a block diagram of an exemplary design flow 100 used forexample, in semiconductor IC logic design, simulation, test, layout, andmanufacture. Design flow 100 includes processes, machines and/ormechanisms for processing design structures or devices to generatelogically or otherwise functionally equivalent representations of thedesign structures and/or devices described above and shown in FIGS.1-11. The design structures processed and/or generated by design flow100 may be encoded on machine-readable transmission or storage media toinclude data and/or instructions that when executed or otherwiseprocessed on a data processing system generate a logically,structurally, mechanically, or otherwise functionally equivalentrepresentation of hardware components, circuits, devices, or systems.Machines include, but are not limited to, any machine used in an ICdesign process, such as designing, manufacturing, or simulating acircuit, component, device, or system. For example, machines mayinclude: lithography machines, machines and/or equipment for generatingmasks (e.g., e-beam writers), computers or equipment for simulatingdesign structures, any apparatus used in the manufacturing or testprocess, or any machines for programming functionally equivalentrepresentations of the design structures into any medium (e.g., amachine for programming a programmable gate array).

Design flow 100 may vary depending on the type of representation beingdesigned. For example, a design flow 100 for building an applicationspecific IC (ASIC) may differ from a design flow 100 for designing astandard component or from a design flow 100 for instantiating thedesign into a programmable array, for example a programmable gate array(PGA) or a field programmable gate array (FPGA) offered by Altera® Inc.or Xilinx® Inc.

FIG. 12 illustrates multiple such design structures including an inputdesign structure 102 that is preferably processed by a design process104. Design structure 102 may be a logical simulation design structuregenerated and processed by design process 104 to produce a logicallyequivalent functional representation of a hardware device. Designstructure 102 may also or alternatively comprise data and/or programinstructions that when processed by design process 104, generate afunctional representation of the physical structure of a hardwaredevice. Whether representing functional and/or structural designfeatures, design structure 102 may be generated using electroniccomputer-aided design (ECAD) such as implemented by a coredeveloper/designer. When encoded on a machine-readable datatransmission, gate array, or storage medium, design structure 102 may beaccessed and processed by one or more hardware and/or software moduleswithin design process 104 to simulate or otherwise functionallyrepresent an electronic component, circuit, electronic or logic module,apparatus, device, or system such as those shown in FIGS. 1-11. As such,design structure 102 may comprise files or other data structuresincluding human and/or machine-readable source code, compiledstructures, and computer-executable code structures that when processedby a design or simulation data processing system, functionally simulateor otherwise represent circuits or other levels of hardware logicdesign. Such data structures may include hardware-description language(HDL) design entities or other data structures conforming to and/orcompatible with lower-level HDL design languages such as Verilog andVHDL, and/or higher level design languages such as C or C++.

Design process 104 preferably employs and incorporates hardware and/orsoftware modules for synthesizing, translating, or otherwise processinga design/simulation functional equivalent of the components, circuits,devices, or logic structures shown in FIGS. 1-11 to generate a netlist106 which may contain design structures such as design structure 102.Netlist 106 may comprise, for example, compiled or otherwise processeddata structures representing a list of wires, discrete components, logicgates, control circuits, I/O devices, models, etc. that describes theconnections to other elements and circuits in an integrated circuitdesign. Netlist 106 may be synthesized using an iterative process inwhich netlist 106 is resynthesized one or more times depending on designspecifications and parameters for the device. As with other designstructure types described herein, netlist 106 may be recorded on amachine-readable data storage medium or programmed into a programmablegate array. The medium may be a non-volatile storage medium such as amagnetic or optical disk drive, a programmable gate array, a compactflash, or other flash memory. Additionally, or in the alternative, themedium may be a system or cache memory, buffer space, or electrically oroptically conductive devices and materials on which data packets may betransmitted and intermediately stored via the Internet, or othernetworking suitable means.

Design process 104 may include hardware and software modules forprocessing a variety of input data structure types including netlist106. Such data structure types may reside, for example, within libraryelements 108 and include a set of commonly used elements, circuits, anddevices, including models, layouts, and symbolic representations, for agiven manufacturing technology (e.g., different technology nodes, 32 nm,45 nm, 90 nm, etc.). The data structure types may further include designspecifications 110, characterization data 112, verification data 114,design rules 116, and test data files 118 which may include input testpatterns, output test results, and other testing information. Designprocess 104 may further include, for example, standard mechanical designprocesses such as stress analysis, thermal analysis, mechanical eventsimulation, process simulation for operations such as casting, molding,and die press forming, etc. One of ordinary skill in the art ofmechanical design can appreciate the extent of possible mechanicaldesign tools and applications used in design process 104 withoutdeviating from the scope and spirit of the invention. Design process 104may also include modules for performing standard circuit designprocesses such as timing analysis, verification, design rule checking,place and route operations, etc.

Design process 104 employs and incorporates logic and physical designtools such as HDL compilers and simulation model build tools to processdesign structure 102 together with some or all of the depictedsupporting data structures along with any additional mechanical designor data (if applicable), to generate a second design structure 120.Design structure 120 resides on a storage medium or programmable gatearray in a data format used for the exchange of data of mechanicaldevices and structures (e.g., information stored in an IGES, DXF,Parasolid XT, JT, DRG, or any other suitable format for storing orrendering such mechanical design structures). Similar to designstructure 102, design structure 120 preferably comprises one or morefiles, data structures, or other computer-encoded data or instructionsthat reside on transmission or data storage media and that whenprocessed by an ECAD system generate a logically or otherwisefunctionally equivalent form of one or more of the embodiments of theinvention shown in FIGS. 1-11. In one embodiment, design structure 120may comprise a compiled, executable HDL simulation model thatfunctionally simulates the devices shown in FIGS. 1-11.

Design structure 120 may also employ a data format used for the exchangeof layout data of integrated circuits and/or symbolic data format (e.g.,information stored in a GDSII (GDS2), GL1, OASIS, map files, or anyother suitable format for storing such design data structures). Designstructure 120 may comprise information such as, for example, symbolicdata, map files, test data files, design content files, manufacturingdata, layout parameters, wires, levels of metal, vias, shapes, data forrouting through the manufacturing line, and any other data required by amanufacturer or other designer/developer to produce a device orstructure as described above and shown in FIGS. 1-11. Design structure120 may then proceed to a stage 122 where, for example, design structure120: proceeds to tape-out, is released to manufacturing, is released toa mask house, is sent to another design house, is sent back to thecustomer, etc.

The methods as described above are used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case, the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

A feature may be “connected” or “coupled” to or with another element maybe directly connected or coupled to the other element or, instead, oneor more intervening elements may be present. A feature may be “directlyconnected” or “directly coupled” to another element if interveningelements are absent. A feature may be “indirectly connected” or“indirectly coupled” to another element if at least one interveningelement is present.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

1. A method of forming a device structure for a bipolar junction transistor, the method comprising: forming an intrinsic base layer on a semiconductor substrate; forming an etch stop layer on the intrinsic base layer; forming an extrinsic base layer on the etch stop layer; forming a first trench penetrating through the extrinsic base layer to the etch stop layer by etching the extrinsic base layer selective to the etch stop layer; extending the first trench through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer; and after the first trench is extended through the etch stop layer, forming an emitter using the first trench.
 2. The method of claim 1 wherein the intrinsic base layer includes a first sublayer comprised of a first semiconductor material and a second sublayer comprised of a second semiconductor material that etches selectively to the etch stop layer, and forming the intrinsic base layer on the semiconductor substrate comprises: forming the first sublayer on the semiconductor substrate; and forming the second sublayer on the first sublayer.
 3. The method of claim 2 wherein extending the first trench through the etch stop layer comprises: etching the etch stop layer selective to the second sublayer of the intrinsic base layer.
 4. The method of claim 1 further comprising: forming a second trench penetrating through the extrinsic base layer to the etch stop layer; and extending the second trench through the etch stop layer to the intrinsic base layer, wherein the second trench is concurrently formed with the first trench, and the second trench is concurrently extended through the etch stop layer with the first trench.
 5. The method of claim 4 further comprising: after the emitter is formed in the first trench, extending the second trench through the intrinsic base layer and into the semiconductor substrate; and forming an isolation region in the semiconductor substrate using the second trench.
 6. The method of claim 5 wherein the emitter includes a head that protrudes out of the first trench, and further comprising: before the etch stop layer is etched, forming a protective layer at a sidewall of the head of the emitter and an etch mask on a top surface of the head of the emitter, wherein the etch stop layer and the intrinsic base layer are each etched selective to the protective layer.
 7. The method of claim 6 wherein the protective layer is a doped region having an opposite conductivity type from a bulk of the emitter, and forming the protective layer at the sidewall of the head of the emitter comprises: ion implanting the sidewall of the head of the emitter to define the doped region.
 8. The method of claim 6 wherein the protective layer is a dielectric spacer, and forming the protective layer at the sidewall of the head of the emitter comprises: forming the dielectric spacer on the sidewall of the head of the emitter.
 9. The method of claim 1 wherein the intrinsic base layer, the etch stop layer, and the extrinsic base layer are formed by a single epitaxial growth.
 10. A method of forming a device structure for a bipolar junction transistor, the method comprising: forming an intrinsic base layer on a semiconductor substrate; forming an extrinsic base layer on the intrinsic base layer; forming a trench penetrating through the extrinsic base layer to the intrinsic base layer by etching the extrinsic base layer selective to the intrinsic base layer; and after the trench is formed, forming an emitter in the trench.
 11. The method of claim 10 wherein the intrinsic base layer includes a first sublayer comprised of a first semiconductor material that etches selectively to the extrinsic base layer and a second sublayer comprised of a second semiconductor material, and forming the intrinsic base layer on the semiconductor substrate comprises: forming the first sublayer on the semiconductor substrate; and forming the second sublayer on the first sublayer.
 12. The method of claim 11 wherein forming the trench comprises: etching through the first sublayer within the trench; and stopping on the second sublayer.
 13. The method of claim 11 further comprising: epitaxially growing the first sublayer within the trench, wherein the emitter is formed after the first sublayer is epitaxially grown within the trench. 14-20. (canceled) 